1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and, more particularly, to a gate array semiconductor integrated circuit such as a gate array LSI.
2. Description of the Related Art
In a conventional gate array LSI, a plurality of bias circuits and a plurality of input/output cells, a predetermined number of input/output circuits of which are formed by an aluminum master slice, are arranged around an internal CMOS logic gate. The input/output circuits include a predetermined number of ECL input and ECL output circuits. Each bias circuit is arranged beforehand at a predetermined position on a chip to generate a bias voltage for obtaining a constant current and a bias voltage to be compared with an input signal and to supply these bias voltages to the input circuit and the output circuit respectively. An input/output cell portion excluding the bias circuits, therefore, can be used as the input or output circuits.
A predetermined number of conventional bias circuits are arranged beforehand regardless of the number of the input/output circuits before the input/ output circuits are arranged, because large current drive ability is required. However, some bias circuits are often not used depending on the layout of the input/output circuits, and therefor redundancy in circuit design cannot be inevitably avoided in conventional circuits. The bias circuits are arranged at fixed positions and cannot perform input/output operations of other signals, resulting in inconvenience.